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1 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller EM78911 i.general description the EM78911 is an 8-bit cid (call identification) risc type microprocessor with low power , high speed cmos technology . integrated onto a single chip are on_chip watchdog (wdt) , ram , rom , programmable real time clock /counter , internal interrupt , power down mode , lcd driver , fsk decoder ,call waiting decoder, dtmf generator and tri-state i/o . the EM78911 provides a single chip solution to design a cid of calling message_display . ii.feature cpu ? operating voltage range : 2.5v ? 5.5v ? 16k 13 on chip rom ? 2.8k 8 on chip ram ? up to 36 bi-directional tri-state i/o ports ? 8 level stack for subroutine nesting ? 8-bit real time clock/counter (tcc) ? two sets of 8 bit counters can be interrupt sources ? selective signal sources and trigger edges , and with overflow interrupt ? programmable free running on chip watchdog timer ? 99.9 single instruction cycle commands ? four modes (internal clock 3.579mhz) 1. sleep mode : cpu and 3.579mhz clock turn off, 32.768khz clock turn off 2. idle mode : cpu and 3.579mhz clock turn off, 32.768khz clock turn on 3. green mode : 3.579mhz clock turn off, cpu and 32.768khz clock turn on 4. normal mode : 3.579mhz clock turn on , cpu and 32.768khz clock turn on ? ring on voltage detector and low battery detector ? input port wake up function ? 9 interrupt source , 4 external , 5 internal ? 100 pin qfp or chip ? port key scan function ? clock frequency 32.768khz ? eight r-option pins cid ? operation volltage 3.5 ? 6v for fsk ? operation volltage 2.5 ? 6v for dtmf ? bell 202 , v.23 fsk demodulator ? dtmf generator ? ring detector on chip call waiting ? operation volltage 3.6 ? 5.5v ? compatible with bellcore special report sr-tsv-002476 ? call-waiting (2130hz plus 2750hz) alert signal detector ? good talkdown and talkoff performance ? sensitivity compensated by adjusting input op gain lcd ? lcd operation voltage chosen by software ? common driver pins : 16 ? segment driver pins : 60 ? 1/4 bias
2 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller ? 1/8,1/16 duty iii.application 1. adjunct units 2. answering machines 3. feature phones iv.pin configuration fig1. pin assignment otp writer pin name mask rom pin name p.s. 1.vdd vdd,avdd 2.vpp /reset 3.dinck p77 4.aclk p76 5.pgmb p75 6.oeb p74 7.data p73 8.gnd vss,avss avss dtmf pllc ringtime rdet1 ring tip gain cwtip xin xout avdd com7 com6 com5 com4 com3 com2 com1 com0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 vss test com8/p60 com9/p61 com10/p62 com11/p63 com12/p64 com13/p65 com14/p66 com15/p67 seg40/p54 seg41/p55 seg42/p56 seg43/p57 seg44/p80 seg45/p81 seg46/p82 seg47/p83 seg48/p84 seg49/p85 seg50/p86 seg51/p87 seg52/p90 seg53/p91 seg54/p92 seg55/p93 seg56/p94 seg57/p95 seg58/p96 seg59/p97 p70/int0 p71/int1 p72/int2 p73/int3 p74 p75 p76 p77 /reset vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
3 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller v.functional block diagram fig2. block diagram1 fig3. block diagram2 cpu cpu timing control timing control timer timer rom rom ram ram lcd driver lcd driver lcd io port io port i/o fsk dtmf call waiting fsk dtmf call waiting xin xout oscillator timing control control sleep and wake-up on i/o port r1(tcc) wdt timer prescalar general ram r4 interruption control rom instruction register instruction decoder r2 stack alu acc r3 r5 data & control bus 2.5k ram port6 ioc6 r6 p60~p67 port7 ioc7 r7 p70~p77 port8 ioc8 r8 p80~p87 port9 ioc9 r9 p90~p97 port5 ioc5 r5 p54~p57 fsk dtmf call waiting
4 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vi.pin descriptions pin i/o description vdd avdd power digital power analog power gnd avss power digital ground analog ground xtin i input pin for 32.768 khz oscillator xtout o output pin for 32.768 khz oscillator com0..com7 com8..com15 o o (port6) common driver pins of lcd drivers seg0...seg43 seg44..seg51 seg52..seg59 o o (port8) o (port9) segment driver pins of lcd drivers port9 as function key can wake up watchdog. pllc i phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with avss tip i should be connected with tip side of twisted pair lines for fsk. ring i should be connected with ring side of twisted pair lines for fsk. cwtip i should be connected with tip side of twisted pair lines for cw. gain i op output pin for gain adjustment. rdet1 i detect the energy on the twisted pair lines . these two pins coupled to the twisted pair lines through an attenuating network. /ring time i determine if the incoming ring is valid.an rc network may be connected to the pin. int0 int1 int2 int3 port7(0) port7(1) port7(2) port7(3) port7(4:7) port7(0)~port7(3) signal can be interrupt signals. int2 and int3 has the same interrupt flag. io port p5.4 ~p5.7 port5 port 5 can be input or output port each bit. shared with lcd segment signals p6.0 ~p6.7 port6 port 6 can be input or output port each bit. shared with lcd common signals p7.0 ~p7.7 port7 port 7 can be input or output port each bit. internal pull high function. key scan function. p8.0 ~p8.7 port8 port 8 can be input or output port each bit. and shared with segment signal. p9.0 ~p9.7 port9 port 9 can be input or output port each bit. and can be set to wake up watch dog timer. and shared with segment signal. test i test pin into test mode , normal low dtmf o dtmf tone output reset i
5 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.functional descriptions vii.1 operational registers 1. r0 (indirect addressing register) * r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). 2. r1 (tcc) * increased by an external signal edge applied to tcc , or by the instruction cycle clock. written and read by the program as any other register. 3. r2 (program counter) * the structure is depicted in fig. 4. * generates 16k 13 on-chip rom addresses to the relative programming instruction codes. * "jmp" instruction allows the direct loading of the low 10 program counter bits. * "call" instruction loads the low 10 bits of the pc, pc+1, and then push into the stack. * "ret'' ("retl k", "reti") instruction loads the program counter with the contents at the top of stack. * "mov r2,a" allows the loading of an address from the a register to the pc, and the ninth and tenth bits are cleared to "0''. * "add r2,a" allows a relative address be added to the current pc, and contents of the ninth and tenth bits are cleared to "0''. * "tbl" allows a relative address be added to the current pc, and contents of the ninth and tenth bits don't change. the most significant bit (a10~a13) will be loaded with the content of bit ps0~ps3 in the status register (r5) upon the execution of a "jmp'', "call'', "add r2,a'', or "mov r2,a'' instruction. fig.4 program counter organization pc a13 a12 a11 a10 a9 a8 a7~a0 0000 page0 0000~03ff 0001 page1 0400~07ff 1110 page14 3800~3bff 1111 page15 3c00~3fff 0010 page3 0800~0bff stack1 stack2 stack3 stack4 stack5 stack6 stack7 stack8 call ret retl reti
6 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller fig.5 data memory configuration 4. r3 (status register) 7 6 5 4 3 2 1 0 cas page - t p z dc c * bit 0 (c) carry flag * bit 1 (dc) auxiliary carry flag * bit 2 (z) zero flag * bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. * bit 4 (t) time-out bit. set to 1 by the "slep" and "wdtc" command, or during power up and reset to 0 by wdt timeout. event t p remark wdt wake up from sleep mode 0 0 wdt time out (not sleep mode) 0 1 /reset wake up from sleep 1 0 power up 1 1 low pulse on /reset x x x .. don't care * bit 5 unused * bit 6 page : change iocb ~ ioce to another page , 0/1 => page0 / page1 * bit7 (cas : call waiting output) 0/1= cw data valid/no data 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f r0 r1(tcc) r2(pc) r3(status) r4(rsr) r5(rom page & r5) r6(port6) r7(port7) r8(port8) r9(port9) ra(clk,fsk) rb(dtmf) rc(2.5k ram address) rd(2.5k ram data) re(wdt) rf(int flag) 10 : 1f 16x8 common register 20 : 3f bank0 ~bank3 32x8 ~32x8 register ioc6 ioc7 ioc8 ioc9 ioca iocb(lcd address) iocc(lcd data) iocd(pull high) ioce(io, lcd) iocf(int control) iocb(counter1) iocc(counter2) iocd(r-option) page0 page1 bank1 bank2 ????..bank10 256x8 256x8 ?????.256x8 rc(address) rd(data) 0 : 255 address register control register (page0) control register (page1)
7 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller 5. r4 (ram select register) * bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode. * bits 6 ~ 7 determine which bank is activated among the 4 banks. * see the configuration of the data memory in fig. 5. 6. r5 (program page select register) 7 6 5 4 3 2 1 0 r57 r56 r55 r54 ps3 ps2 ps1 ps0 * bit 0 (ps0) ~ 3 (ps3) page select bits page select bits ps3 ps2 ps1 ps0 program memory page (address) 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 0 1 1 0 page 6 0 1 1 1 page 7 1 0 0 0 page 8 1 0 0 1 page 9 1 0 1 0 page 10 1 0 1 1 page 11 1 1 0 0 page 12 1 1 0 1 page 13 1 1 1 0 page 14 1 1 1 1 page 15 *user can use page instruction to change page. to maintain program page by user. otherwise, user can use far jump (fjmp) or far call (fcall) instructions to program user's code. and the program page is maintained by emc's complier. it will change user's program by inserting instructions within program. *bit4~7 : port5 4-bit i/o register 6. r6 ~ r9 (port 6 ~ port 9) * four 8-bit i/o registers. 7. ra (fsk status register)(bit 0,1,2,4 read only) 7 6 5 4 3 2 1 0 idle /358e /lpd /low_bat /fskpwr data /cd /rd * bit0 (read only) (ring detect signal) 0/1 : ring valid/ring invalid * bit1(read only)(carrier detect signal) 0/1 : carrier valid/carrier invalid * bit2(read only)(fsk demodulator output signal) fsk data transmitted in a baud rate 1200 hz. * bit3(read/write)(fsk block power up signal) 1/0 : fsk demodulator block power up/fsk demodulator power down
8 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller * the relation between bit0 to bit3 is shown in fig.6. sleep mode sleep mode sleep mode sleep mode wake up wake up wake up wake up mode mode mode mode /ringtime ='0' /ringtime ='0' /ringtime ='0' /ringtime ='0' fsk decoder fsk decoder fsk decoder fsk decoder begin its work begin its work begin its work begin its work /fskpwr='1' /fskpwr='1' /fskpwr='1' /fskpwr='1' data transfer data transfer data transfer data transfer to micro to micro to micro to micro /rd and /cd ='1' and /rd and /cd ='1' and /rd and /cd ='1' and /rd and /cd ='1' and nothing to do for 30 nothing to do for 30 nothing to do for 30 nothing to do for 30 sec , /fskpwr='0' sec , /fskpwr='0' sec , /fskpwr='0' sec , /fskpwr='0' or external keys or external keys or external keys or external keys pressed pressed pressed pressed /rd and /cd ='1' /rd and /cd ='1' /rd and /cd ='1' /rd and /cd ='1' sleep mode sleep mode sleep mode sleep mode begin begin begin begin set /fskpwr='0' set /fskpwr='0' set /fskpwr='0' set /fskpwr='0' /ringtime ='0' /ringtime ='0' /ringtime ='0' /ringtime ='0' or external keys or external keys or external keys or external keys pressed pressed pressed pressed wake up mode wake up mode wake up mode wake up mode 8-bit wake up and 8-bit wake up and 8-bit wake up and 8-bit wake up and set /fskpwr='1' set /fskpwr='1' set /fskpwr='1' set /fskpwr='1' accept data from accept data from accept data from accept data from fsk decoder fsk decoder fsk decoder fsk decoder /rd and /cd ='1' /rd and /cd ='1' /rd and /cd ='1' /rd and /cd ='1' data end and 30 data end and 30 data end and 30 data end and 30 sec nothing to do. sec nothing to do. sec nothing to do. sec nothing to do. yes yes yes yes no no no no no no no no yes yes yes yes state diagram between 8-bit state diagram between 8-bit state diagram between 8-bit state diagram between 8-bit and fsk decoder and fsk decoder and fsk decoder and fsk decoder flow diagram between 8-bit flow diagram between 8-bit flow diagram between 8-bit flow diagram between 8-bit and fsk decoder and fsk decoder and fsk decoder and fsk decoder fig6. the relation between bit0 to bit3. * bit4(read only)(low battery signal) 0/1 = battery voltage is low/normal . if the vdd voltage is under low power range (controlled by ioca bit0) then sends a '0' signal to /low_bat bit or a '1' signal to this bit. * bit5(read/write)(low battery detect enable) 0/1 = low battery detect disable/enable. the relation between /lpd,/povd and /low_bat can see fig7. vdd vdd vdd vdd vref vref vref vref s2 s2 s2 s2 1 on 1 on 1 on 1 on 0 off 0 off 0 off 0 off s2 s2 s2 s2 1 on 1 on 1 on 1 on 0 off 0 off 0 off 0 off 1 on 1 on 1 on 1 on to low bat to low bat to low bat to low bat to reset to reset to reset to reset /povd /povd /povd /povd /lpd /lpd /lpd /lpd /lpd /lpd /lpd /lpd + + + + - - - - 1 on 1 on 1 on 1 on fig7. the relation between /lpd,/povd * bit6(read/write)(pll enable signal) 0/1=disable/enable the relation between 32.768k and 3.579m can see fig8. fig8. the relation between 32.768k and 3.579k . sub-clock 32.768k h z pll 3.579m h z ra bit6 sw itc h t o system clock 1 0
9 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller * bit7 idle: sleep mode selection bit 0/1=sleep mode/idle mode. this bit will decide slep instruction which mode to go. these two modes can be waken up by tcc clock or watch dog or port9 and run from ?slep? next instruction. wakeup signal sleep mode idle mode green mode normal mode ra(7,6)=(0,0) + slep ra(7,6)=(1,0) + slep ra(7,6)=(x,0) no slep ra(7,6)=(x,1) no slep tcc time out x wake-up + interrupt + next instruction interrupt interrupt wdt time out reset wake-up + next instruction reset reset port9 /ringtime pin reset wake-up + next instruction x x port70~73 x wake-up + interrupt + next instruction interrupt interrupt *p70 ~ p73 's wakeup function is controlled by iocf(1,2,3) and eni instruction. *p70 's wakeup signal is a rising or falling signal defined by cont register bit7. */ringtime pin , port9 ,port71,port72 and port73 's wakeup signal is a falling edge signal. 8. rb(dtmf tone row and column register) (read/write) 7 6 5 4 3 2 1 0 c7 c6 c5 c4 r3 r2 r1 r0 * bit 0 - bit 3 are row-frequency tone. * bit 4 - bit 7 are column-frequency tone. * initial rb is equal to high. bit 7 ~ 0 are all "1" , turn off dtmf power . bit 3~0 row freq 1110 699.2hz 1 2 3 a 1101 771.6hz 4 5 6 b 1011 854hz 7 8 9 c 0111 940.1hz * 0 # d column freq 1203hz 1331.8hz 1472hz 1645.2hz bit 7~4 1110 1101 1011 0111 9. rc(caller id address)(read/write) 7 6 5 4 3 2 1 0 cida7 cida6 cida5 cida4 cida3 cida2 cida1 cida0 * bit 0 ~ bit 7 select caller id ram address up to 256. 10. rd(caller id ram data)(read/write) * bit 0 ~ bit 8 are caller id ram data transfer register. user can see ioca register how to select cid ram banks.
10 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller 11. re(lcd driver,wdt control)(read/write) 7 6 5 4 3 2 1 0 cwpwr /wdte /wup9h /wup9l /wuring lcd_c2 lcd_c1 lcd_m * bit0 (lcd_m):lcd_m decides the methods, including duty, bias, and frame frequency. * bit1~bit2 (lcd_c#):lcd_c# decides the lcd display enable or blanking. change the display duty must set the "lcd_c2,lcd_c1" to "00". lcd_c2,lcd_c1 lcd display control lcd_m duty bias 0 0 change duty disable(turn off lcd) 0 1 1/16 1/4 1/8 1/4 0 1 blanking : : 1 1 lcd display enable : : * bit3 (/wuring, ring wake up enable): used to enable the wake-up function of /ringtime input pin. (1/0=enable/disable) * bit4 (/wup9l, port9 low nibble wake up enable): used to enable the wake-up function of low nibble in port9.(1/0=enable/disable) * bit5 (/wup9h, port9 high nibble wake up enable): used to enable the wake-up function of high nibble in port9.(1/0=enable/disable) * bit6 (/wdte,watch dog timer enable) control bit used to enable watchdog timer.(1/0=enable/disable) the relation between bit3 to bit6 can see the diagram 9. * bit7(power control of call waiting circuit) .(1/0=enable circuit /disable circuit) please enable pll before enable call waiting circuit. /wuring /wuring /wuring /wuring /ringtime /ringtime /ringtime /ringtime /wup9l /wup9l /wup9l /wup9l port9(3:0) port9(3:0) port9(3:0) port9(3:0) /wup9h /wup9h /wup9h /wup9h port9(7:4) port9(7:4) port9(7:4) port9(7:4) /wdte /wdte /wdte /wdte /wdten 0/1=enable/disable /wdten 0/1=enable/disable /wdten 0/1=enable/disable /wdten 0/1=enable/disable fig.9 wake up function and control signal 12. rf (interrupt status register) 7 6 5 4 3 2 1 0 int3 fsk/cw c8_2 c8_1 int2 int1 int0 tcif * "1" means interrupt request, "0" means non-interrupt * bit 0 (tcif) tcc timer overflow interrupt flag. set when tcc timer overflows . * bit 1 (int0) external int0 pin interrupt flag . * bit 2 (int1) external int1 pin interrupt flag . * bit 3 (int2) external int2pin interrupt flag . * bit 4 (c8_1) internal 8 bit counter interrupt flag . * bit 5 (c8_2) internal 8 bit counter interrupt flag . * bit 6 ( fsk/cw ) fsk data or call waiting data interrupt flag * bit 7 (int3) external int3 pin interrupt flag. * high to low edge trigger , refer to the interrupt subsection. * iocf is the interrupt mask register. user can read and clear.
11 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller 13. r10~r3f (general purpose register) * r10~r3f (banks 0~3) all are general purpose registers. vii.2 special purpose registers 1. a (accumulator) * internal data transfer, or instruction operand holding * it's not an addressable register. 2. cont (control register) 7 6 5 4 3 2 1 0 int_edge int ts te pab psr2 psr1 psr0 * bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 * bit 3 (pab) prescaler assignment bit. 0/1 : tcc/wdt * bit 4 (te) tcc signal edge 0: increment from low to high transition on tcc 1: increment from high to low transition on tcc * bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: 16.384khz * bit 6 : (int) int enable flag 0: interrupt masked by disi or hardware interrupt 1: interrupt enabled by eni/reti instructions * bit 7 : int_edge 0:p70 's interruption source is a rising edge signal. 1:p70 's interruption source is a falling edge signal. * cont register is readable and writable.
12 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller 3. ioc5 (i/o port control register) 7 6 5 4 3 2 1 0 ioc57 ioc56 ioc55 ioc54 0 0 0 p5s * bit0: p5s is switch register for i/o port or lcd signal switching. 0/1= normal i/o port/segment output . * bit1~3: unused * bit 4 to bit7 are port5 i/o direction control registers. * "1" put the relative i/o pin into high impedance, while "0" put the relative i/o pin as output. 4. ioc6 ~ ioc9 (i/o port control register) * four i/o direction control registers. * "1" put the relative i/o pin into high impedance, while "0" put the relative i/o pin as output. * user can see iocb register how to switch to normal i/o port. 5. ioca (caller id ram,io ,page control register)(read/write,initial "00000000") 7 6 5 4 3 2 1 0 p8sh p8sl 0 call_4 call_3 call_2 call_1 range * bit0 : register to control low power detection range . 0/1=3.2v/3.6v * bit4~bit1:"000" to "1001" are ten blocks of caller id ram area. user can use 2.5k ram with rd ram address. * bit 5 unused * bit6: port8 low nibble switch, 0/1= normal i/o port/segment output . * bit7: port8 high nibble switch , 0/1= normal i/o port/segment output 6. iocb (lcd address) page0 : bit6 ~ bit0 = lcda6 ~ lcda0 the lcd display data is stored in the data ram . the relation of data area and com/seg pin is as below: com15 ~ com8 com7 ~ com0 40h (bit15 ~ bit8) 00h (bit7 ~ bit0) seg0 41h 01h seg1 : : : : : : : : : : : : 7ah 4ah seg58 7bh 3bh seg59 7ch 3ch empty : : : 7fh 3fh empty page1 : 8 bit up-counter (counter1) preset and read out register . ( write = preset ) . after a interruption , it will count from ?00?.
13 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller 7. iocc (lcd data) page0 : bit7 ~ bit0 = lcd ram data register page1 : 8 bit up-counter (counter2) preset and read out register . ( write = preset) after a interruption , it will count from ?00?. 8. iocd (pull-high control register) page0: 7 6 5 4 3 2 1 0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 * bit 0 ~ 7 (/ph#) control bit used to enable the pull-high of port7(#) pin. 1: enable internal pull-high 0: disable internal pull-high page1: 7 6 5 4 3 2 1 0 ro7 ro6 ro5 ro4 ro3 ro2 ro1 ro0 * bit 7 ~ 0 (ro7~0) control bit used to enable the r-option of port97~port90 pin. 1: enable 0: disable ro is used for r-option . setting ro to ?1? will enable the status of r-option pin (p90 ~ p97) to read by controller. clearing ro will disable r-option function. if the r-option function is used, user must connect port9 pins to gnd by 560k external register . if the register is connected/disconnected , the r9 will read as ? 0/1? when ro is set to ?1?. 9. ioce (bias,pll control register) page0 : 7 6 5 4 3 2 1 0 p9sh p9sl p6s bias3 bias2 bias1 0 sc * bit 0 :sc (scan key signal ) 0/1 = disable/enable. once you enable this bit , all of the lcd signal will have a low pulse during a common period. this pulse has 30us width. please use the procedure to implement the key scan function. a. set port7 as input port b. set iocd page0 port7 pull high c. enable scan key signal d. once push a key . set ra(6)=1 and switch to normal mode. e. blank lcd. disable scan key signal. f. set p6s =0. port6 sent probe signal to port7 and read port7. get the key. g. note!! a probe signal should be delay a instruction at least to another probe signal. h. set p6s =1. port6 as lcd signal. enable lcd.
14 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller fig.10. key scan circuit fig.11.key scan signal * bit 1 :port7 pull high register option. please use default value. p70 p71 p72 p73 p60 p61 p62 p63 key1 key2 key5 key3 key4 com2 seg vdd v1 v2 v3 vlcd gnd vdd v1 v2 v3 vlcd gnd 30us
15 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller * bit 2~4 (bias1~bias3) control bits used to choose lcd operation voltage . lcd operate voltage vop (vdd 5v) vdd=5v 000 001 010 011 100 101 110 111 0.60vdd 0.66vdd 0.74vdd 0.82vdd 0.87vdd 0.93vdd 0.96vdd 1.00vdd 3.0v 3.3v 3.7v 4.0v 4.4v 4.7v 4.8v 5.0v * bit5:port6 switch , 0/1= normal i/o port/common output * bit6:port9 low nibble switch , 0/1= normal i/o port/segment output . bit7:port9 high nibble switch page1 : 7 6 5 4 3 2 1 0 op77 op76 c2s c1s psc1 psc0 cdrd 0 * bit0: unused * bit1: cooked data or raw data select bit , 0/1 ==> cooked data/raw data * bit3~bit2: counter1 prescaler , reset=(0,0) (psc1,psc0) = (0,0)=>1:1 , (0,1)=>1:4 , (1,0)=>1:8 , (1,1)=>reserved * bit4:counter1 source , (0/1)=(32768hz/3.579mhz if enable) scale=1:1 * bit5:counter2 source , (0/1)=(32768hz/3.579mhz if enable) scale=1:1 * bit6:p76 opendrain control (0/1)=(disable/enable) * bit7:p77 opendrain control (0/1)=(disable/enable) 10. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 int3 fsk/cw c8_2 c8_1 int2 int1 int0 tcif * bit 0 ~ 7 interrupt enable bit. 0: disable interrupt 1: enable interrupt * iocf register is readable and writable. vii.3 tcc/wdt prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time. ? an 8 bit counter is available for tcc or wdt determined by the status of the bit 3 (pab) of the cont register. ? see the prescaler ratio in cont register. ? fig. 10 depicts the circuit diagram of tcc/wdt. ? both tcc and prescaler will be cleared by instructions which write to tcc each time. ? the prescaler will be cleared by the wdtc and slep instructions, when assigned to wdt mode.
16 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller ? the prescaler will not be cleared by slep instructions, when assigned to tcc mode. fig. 10 block diagram of tcc wdt vii.4 i/o ports the i/o registers, port 6 ~ port 9, are bi-directional tri-state i/o ports. port 7 can be pulled-high internally by software control. the i/o ports can be defined as "input" or "output" pins by the i/o control registers (ioc6 ~ ioc9 ) under program control. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig.11. fig. 11 the circuit of i/o port and i/o control register 16.38khz
17 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii . 5 reset and wake-up the reset can be caused by (1) power on reset, or voltage detector (2) wdt timeout. (if enabled and in green or normal mode) note that only power on reset, or only voltage detector in case(1) is enabled in the system by code option bit. if voltage detector is disabled, power on reset is selected in case (1). refer to fig. 12. fig. 12 block diagram of reset of controller once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? when power on, the upper 3 bits of r3 and the upper 2 bits of r4 are cleared. ? the watchdog timer and prescaler are cleared. ? the watchdog timer is disabled. ? the cont register is set to all "1" ? the other register (bit7..bit0) r5 = port ioc5 = "11110000" r6 = port ioc6 = "11111111" r7 = port ioc7 = "11111111" r8 = port ioc8 = "11111111" r9 = port ioc9 = "11111111" ra = "x00x0xxx ioca = " 00000000" rb = "11111111" page0 iocb = "00000000" page1 iocb = "00000000" rc = "00000000" page0 iocc = "0 xxxxxxx" page1 iocc = " 00000000" rd = "xxxxxxxx" page0 iocd = " 00000000" page1 iocd = ?00000000? re = "00000000" page0 ioce = "00000000" page1 ioce = "00000000" rf = "00000000" iocf = "00000000" the controller can be awakened from sleep mode or idle mode (execution of "slep" instruction, named as sleep mode or idle mode) by (1)tcc time out (2) wdt time-out (if enabled) or, (3) external input at port9. the three cases will cause the controller wake up and run from next instruction. after wake-up , user should control watch dog in case of reset in green mode or normal mode. the last two should be open
18 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller re register before into sleep mode or idle mode . the first one case will set a flag in rf bit0 .but it will not go to address 0x08.
19 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.6 interrupt the caller id ic has internal interrupts which are falling edge triggered, as followed : tcc timer overflow interrupt (internal) , two 8-bit counters overflow interrupt . if these interrupt sources change signal from high to low , then rf register will generate '1' flag to corresponding register if you enable iocf register. rf is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. there are four external interrupt pins including int0 , int1 , int2 , int3 . and four internal interrupt available. internal signals include tcc,cnt1,cnt2,fsk and call waiting data. the last two will generate a interrupt when the data trasient from high to low. external interrupt int0 , int1 , int2 , int3 signals are from port7 bit0 to bit3 . if iocf is enable then these signal will cause interrupt , or these signals will be treated as general input data . after reset, the next instruction will be fetched from address 000h and the instruction inturrept is 001h and the hardware inturrept is 008h. tcc will go to address 0x08 in green mode or normal mode after time out. and it will run next instruction from ?slep? instruction. these two cases will set a rf flag. it is very important to save acc,r3 and r5 when processing a interruption. address instruction note 0x08 disi ;disable interrupt 0x09 mov a_buffer,a ;save acc 0x0a swap a_buffer 0x0b swapa 0x03 ;save r3 status 0x0c mov r3_buffer,a 0x0d mov a,0x05 ;save rom page register 0x0e mov r5_buffer,a : : : : : mov a,r5_buffer ;return r5 : mov 0x05,a : swapa r3_buffer ;return r3 : mov 0x03,a : swapa a_buffer ;return acc : reti vii.7 instruction set instruction set has the following features: (1). every bit of any register can be set, cleared, or tested directly. (2). the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register.
20 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller the symbol "r" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "r'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. instruction binary hex mnemonic operation status affecte d 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a cont none 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 wdt t,p 0 0000 0000 rrrr 000r iow r a iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] pc none 0 0000 0001 0011 0013 reti [top of stack] pc enable interrupt none 0 0000 0001 0100 0014 contr cont a none 0 0000 0001 rrrr 001r ior r iocr a none 0 0000 0010 0000 0020 tbl r2+a r2 bits 9,10 do not clear z,c,dc 0 0000 01rr rrrr 00rr mov r,a a r none 0 0000 1000 0000 0080 clra 0 a z 0 0000 11rr rrrr 00rr clr r 0 r z 0 0001 00rr rrrr 01rr sub a,r r-a a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 a z 0 0001 11rr rrrr 01rr dec r r-1 r z 0 0010 00rr rrrr 02rr or a,r a v r a z 0 0010 01rr rrrr 02rr or r,a a v r r z 0 0010 10rr rrrr 02rr and a,r a & r a z 0 0010 11rr rrrr 02rr and r,a a & r r z 0 0011 00rr rrrr 03rr xor a,r a r a z 0 0011 01rr rrrr 03rr xor r,a a r r z 0 0011 10rr rrrr 03rr add a,r a + r a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r a z 0 0100 01rr rrrr 04rr mov r,r r r z 0 0100 10rr rrrr 04rr coma r /r a z 0 0100 11rr rrrr 04rr com r /r r z 0 0101 00rr rrrr 05rr inca r r+1 a z 0 0101 01rr rrrr 05rr inc r r+1 r z 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1) r(0) c, c a(7) c 0 0110 01rr rrrr 06rr rrc r r ( n ) r ( n-1 ) c
21 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller r(0) c, c r(7) 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1) r(7) c, c a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1) r(7) c, c r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7) r(4-7) a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 0 100b bbrr rrrr 0 xxx bc r,b 0 r(b) none 0 101b bbrr rrrr 0 xxx bs r,b 1 r(b) none 0 110b bbrr rrrr 0 xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0 xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 [sp] (page, k) pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1001 kkkk kkkk 19kk or a,k a k a z 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1100 kkkk kkkk 1ckk retl k k a, [top of stack] pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a a z,c,dc 1 1110 0000 0001 1e01 int pc+1 [sp] 001h pc none 1 1110 1000 kkkk 1e8k page k k->r5(3:0) none 1 1111 kkkk kkkk 1fkk add a,k k+a a z,c,dc vii.8 code option register the caller id ic has one code option register which is not part of the normal program memory. the option bits cannot be accessed during normal program execution. 7 6 5 4 3 2 1 0 - - - - - - /povd mclk * bit 0 : main clock selection. 0/1 = 3.58mhz / 1.84mhz main clock selection. 0/1 = 3.58mhz / 1.84mhz main clock selection. 0/1 = 3.58mhz / 1.84mhz main clock selection. 0/1 = 3.58mhz / 1.84mhz * bit 1 :(/povd) : power on voltage detector. 0: enable 1: disable /povd 2.2v reset power on reset low power detect without reset low power detect controlled by ra(5) sleep mode current 1 no yes yes yes 1ua 0 yes yes yes yes 15ua * bits 2~7 : unused, must be "0"s. vii.9 fsk function
22 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.9.1 functional block diagram fig13. fsk block diagram vii.9.2 function descriptions the caller id ic is a cmos device designed to support the caller number deliver feature which is offered by the regional bell operating companies.the fsk block comprises two paths: the signal path and the ring indicator path. the signal path consist of an input differential buffer,a band pass filter, an fsk demodulator and a data valid with carrier detect circuit. the ring detector path includes a clock generator, a ring detect circuit . in a typical application, the ring detector maintains the line continuously while all other functions of the chip are inhibited. if a ring signal is sent, the /ringtime pin will has a low signal. user can use this signal to wake up whole chip or read /rd signal from ra register. a /fskpwr input is provided to activate the block regardless of the presence of a power ring signal. if /fskpwr is sent low, the fsk block will power down whenever it detects a valid ring signal, it will power on when /fskpwr is high. the input buffer accepts a differential ac coupled input signal through the tip and ring input and feeds this signal to a band pass filter. once the signal is filtered, the fsk demodulator decodes the information and sends it to a post filter. the output data is then made available at data out pin. this data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date , time and calling number. if no data is present, the data out pin is held in a high state. this is accomplished by an carrier detect circuit which determines if the in-band energy is high enough. if the incoming signal is valid and thus the demodulated data is transferred to data out pin . if it is not, then the fsk demodulator is blocked. vii.9.3 ring detect circuit when vdd is applied to the circuit, the rc network will charge cap c1 to vdd holding /ring time off . the resistor network r2 to r3 attenuates the incoming power ring applied to the top of r2. the values given ring det circuit ring det1 tip ring power up fsk demodul data valid energy det circuit data out /cd clock osc in osc out /rd /ring time band pass filter /fskpwr
23 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller have been chosen to provide a sufficient voltage at det1 pin, to turn on the schmitt trigger input. when vt+ of the schmitt is exceeded, cap c1 will discharge. the value of r1 and c1 must be chosen to hold the /ring time pin voltage below the vt+ of the schmitt between the individual cycle of the power ring. with /ringtime enabled, this signal will be a /rd signal in ra throught a buffer. fig14. ring detect circuit vii.10 dtmf ( dual tone multi frequency ) tone generator built-in dtmf generator can generate dialing tone signals for telephone of dialing tone type. there are two kinds of dtmf tone . one is the group of row frequency, the other is the group of column frequency, each group has 4 kinds of frequency , user can get 16 kinds of dtmf frequency totally. dtmf generator contains a row frequency sine wave generator for generating the dtmf signal which selected by low order 4 bits of rb and a column frequency sine wave generator for generating the dtmf signal which selected by high order 4 bits of rb. this block can generate single tone by filling one bit zero to this register. if all the values are high , the power of dtmf will turn off until one or two low values. either high or low 4 bits must be set by an effective value, otherwise, if any ineffective value or both 4 bits are load effective value, tone output will be disable. recommend value refer to table as follow please : system clock system clock system clock system clock dtmf low-freq dtmf low-freq dtmf low-freq dtmf low-freq selection selection selection selection dtmf high-freq dtmf high-freq dtmf high-freq dtmf high-freq selection selection selection selection sine wave sine wave sine wave sine wave generator generator generator generator sine wave sine wave sine wave sine wave generator generator generator generator adder adder adder adder row row row row register register register register column column column column register register register register low frequency generator low frequency generator low frequency generator low frequency generator high frequency generato r high frequency generato r high frequency generato r high frequency generato r dtmf to ne dtmf to ne dtmf to ne dtmf to ne output output output output vdd /ring time det1 /rd c1 r3 r1 r2 /ring time
24 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller fig15. dtmf block diagram * rb ( dtmf register ) . bit 0 - bit 3 are row-frequency tone. . bit 4 - bit 7 are column-frequency tone. . initial rb is equal to high. . except below values of rb ,the other values of rb are not effect. if rb is set by ineffective value, the dtmf output will be disable and there is no tone output. . bit 7 ~ 0 are all "1" , turn off dtmf power . bit 3~0 row freq 1110 699.2hz 1 2 3 a 1101 771.6hz 4 5 6 b 1011 854hz 7 8 9 c 0111 940.1hz * 0 # d column freq 1203hz 1331.8hz 1472hz 1645.2hz bit 7~4 1110 1101 1011 0111 vii.11 lcd driver the caller id ic can drive lcd directly and has 60 segments and 16 commons that can drive 60*16 dots totally. lcd block is made up of lcd driver , display ram, segment output pins , common output pins and lcd operating power supply pins. duty , bias , the number of segment , the number of common and frame frequency are determined by lcd mode register . lcd control register. the basic structure contains a timing control which uses the basic frequency 32.768khz to generate the proper timing for different duty and display access. re register is a command register for lcd driver, the lcd display( disable, enable, blanking) is controlled by lcd_c and the driving duty and bias is decided by lcd_m and the display data is stored in data ram which address and data access controlled by registers iocb and iocc. fig16. lcd driver control lcd timing control re(lcd_c,lcd_m) bias control vdd-vlcd lcd duty control lcd common control com ram iocb(address) iocc(data) display data control lcd segment control seg 32.768khz
25 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.11.1 lcd driver control re(lcd driver control)(initial state "00000000") 7 6 5 4 3 2 1 0 - - - - - lcd_c2 lcd_c1 lcd_m *bit0 (lcd_m):lcd_m decides the methods, including duty, bias, and frame frequency. *bit1~bit2 (lcd_c#):lcd_c# decides the lcd display enable or blanking. change the display duty must set the lcd_c to "00". lcd_c2,lcd_c1 lcd display control lcd_m duty bias 0 0 change duty disable(turn off lcd) 0 1 1/16 1/4 1/8 1/4 0 1 blanking : : 1 1 lcd display enable : : vii.11.2 lcd display area the lcd display data is stored in the data ram . the relation of data area and com/seg pin is as below: com15 ~ com8 com7 ~ com0 40h (bit15 ~ bit8) 00h (bit7 ~ bit0) seg0 41h 01h seg1 : : : : : : 7bh 3bh seg59 7ch 3ch empty 7dh 3dh empty 7eh 3eh empty 7fh 3fh empty *iocb(lcd display ram address) 7 6 5 4 3 2 1 0 - lcda6 lcda5 lcda4 lcda3 lcda2 lcda1 lcda0 bit 0 ~ bit 6 select lcd display ram address up to 120. lcd ram can be write whether in enable or disable mode and read only in disable mode. *iocc(lcd display data) : bit 0 ~ bit 8 are lcd data. vii.11.3 lcd com and seg signal * com signal : the number of com pins varies according to the duty cycle used, as following: in 1/8 duty mode com8 ~ com15 must be open. in 1/16 duty mode com0 ~ com15 pins must be used. com0 com1 com2 com3 com4 com5 com6 com7 com8 .. com15 1/8 o o o o o o o o x .. x 1/16 o o o o o o o o o .. o x:open,o:select
26 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller * seg signal: the 60 segment signal pins are connected to the corresponding display ram address 00h to 3bh. the high byte and the low byte bit7 down to bit0 are correlated to com15 to com0 respectively . when a bit of display ram is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non- select signal is sent to the corresponding segment pin. *com, seg and select/non-select signal is shown as following: fig.17 lcd wave 1/4 bias vdd v1 v2 v3 vlcd frame com0 com1 com2 seg seg light dark vdd v1 v2 v3 vlcd vdd v1 v2 v3 vlcd vdd v1 v2 v3 vlcd vdd v1 v2 v3 vlcd
27 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.11.4 lcd bias control ioce (bias control register) 7 6 5 4 3 2 1 0 bias3 bias2 bias1 * bit 2~4 (bias1~bias3) control bits used to choose lcd operation voltage . the circuit can refer ti figure15. lcd operate voltage vop (vdd 5v) vdd=5v 000 001 010 011 100 101 110 111 0.60vdd 0.66vdd 0.74vdd 0.82vdd 0.87vdd 0.93vdd 0.96vdd 1.00vdd 3.0v 3.3v 3.7v 4.0v 4.4v 4.7v 4.8v 5.0v * bit 5~7 unused 78810/78910 78810/78910 78810/78910 78810/78910 vdd vdd vdd vdd vlcd vlcd vlcd vlcd vop vop vop vop vss vss vss vss vop=vdd-vlcd vop=vdd-vlcd vop=vdd-vlcd vop=vdd-vlcd r=1k r=1k r=1k r=1k r r r r r r r r r r r r r r r r v1 v1 v1 v1 v2 v2 v2 v2 v3 v3 v3 v3 mux bias3~1 000 001 010 011 100 101 110 111 : : 8.2r 0.4r 0.4r 0.3r 0.3r 0.2r 0.1r 0.1r fig.18 lcd bias circuit
28 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vii.12 call waiting function description fig.19 call waiting block diagram call waiting service works by alerting a customer engaged in a telephone call to a new incoming call. this way the customer can still receive important calls while engaged in a current call. the call waiting decoder can detect cas(call-waiting alerting signal 2130hz plus 2750hz) and generate a valid signal on the data pins. the call waiting decoder is designed to support the caller number deliver feature, which is offered by regional bell operating companies. the call waiting decoder has four blocks, including pre-amplifier, band pass filter, level detect and digital detection algorithm. in a typical application, after enabling cw circuit (by re bit7 cwpwr) this ic receives tip and ring signals from twisted pairs. the signals as inputs of pre-amplifier, and the amplifier sends input signal to a band pass filter. once the signal is filtered, the digital detection block decodes the information and sends it to r3 register bit7 . the output data made available at r3 cas bit. the data is cas signals. the cas is normal high. when this ic detects 2130hz and 2750hz frequency, then cas pin goes to low. cwtip filter digital detection algorithm vdd/2 band pass detect level voltage reference clock generator gain cas 0: data valid 1: data invalid call waiting circuit power control fsk block tip ring - + fsk data
29 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller viii.absolute operation maximum ratings rating symbol value unit dc supply voltage vdd -0.3 to 6 v input voltage vin -0.5 to vdd +0.5 v operating temperature range ta 0 to 70 ix dc electrical characteristic (ta=0 c ~ 70 c, vdd=5v 5%, vss=0v) (vdd=2.5v to 6v for cpu ; vdd=3.5v to 6v for fsk ; vdd=2.5v to 6v for dtmf ) symbol parameter condition min typ max unit iil1 input leakage current for input pins vin = vdd, vss 1 a iil2 input leakage current for bi-directional pins vin = vdd, vss 1 a vih input high voltage 2.5 v vil input low voltage 0.8 v viht input high threshold voltage /reset, tcc, rdet1 2.0 v vilt input low threshold voltage /reset, tcc,rdet1 0.8 v vihx clock input high voltage osci 3.5 v vilx clock input low voltage osci 1.5 v vhscan key scan input high voltage port6 for key scan 3.5 v vlscan key scan input low voltage port6 for key scan 1.5 v voh1 output high voltage (port6,7,8) ioh = -1.6ma 2.4 v (port9) ioh = -6.0ma 2.4 v vol1 output low voltage (port6,7,8) iol = 1.6ma 0.4 v (port9) iol = 6.0ma 0.4 v vcom com voltage drop io=+/- 50 ua - - 2.9 v vseg segment voltage drop io=+/- 50 ua - - 3.8 v vlcd lcd drive reference voltage contrast adjustment iph pull-high current pull-high active input pin at vss -10 -15 a isb1 power down current (sleep mode) all input and i/o pin at vdd, output pin floating, wdt disabled 1 4 a isb2 low clock current (green mode) clk=32.768khz, fsk, dtmf, cw block disable , all input and i/o pin at vdd, output pin floating, wdt disabled, lcd enable 65 80 a isb3 low clock current (idle mode) clk=32.768khz, fsk, dtmf, cw block disable , all input and i/o pin at vdd, output pin floating, wdt disabled, lcd enable 45 60 a
30 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller cpu disable icc operating supply current (normal mode) /reset=high, clk=3.579mhz, output pin floating,lcd enable, fsk, dtmf, cw fblock disable 1.5 1.8 ma ix ac electrical characteristic (ta=0 c ~ 70 c, vdd=5v, vss=0v) symbol parameter conditions min typ max unit dclk input clk duty cycle 45 50 55 % tins instruction cycle time 32.768k 3.579m 60 550 us ns tdrh device delay hold time 18 ms ttcc tcc input period note 1 (tins+20)/n ns twdt watchdog timer period ta = 25 c 18 ms note 1: n= selected prescaler ratio. (fsk band pass filter ac characteristic)(vdd=+5v,ta=+25 ) characteristic min typ max unit input sensitivity tip and ring pin1 and pin2 vdd=+5v -40 -48 -- dbm (call waiting band pass filter ac characteristic) (v dd =+5v,ta=+25 c) characteristic min typ max unit input sensitivity tip and ring pins ,vdd=+5v, input g=1 -38 dbm description symbol min typ max unit osc start up(32.768khz) (3.579mhz pll) tosc -- 300 400 10 ms (fsk ac characteristic) carrier detect low tcdl -- 10 14 ms data out to carrier det low tdoc -- 10 20 ns power up to fsk(setup time) tsup -- 15 20 ms /rd low to ringtime low trd 50 ms end of fsk to carrier detect high tcdh 8 -- -- ms (call waiting ac characteristic) cas input signal length (2130 ,2750 hz @ -20dbm ) tcasi 80 ms data detect delay time td 42 ms data release time tr 26 ms
31 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller xi. timing diagrams ` fig.20 ac timing
32 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller fig.21 fsk timing diagram fig.22 call waiting timing diagram pcw power power off power on on/off events td plug in on hook in use cas tcasi cas tr normal tip/ring /ring time /rd /cd data osc first ring 2 seconds 0.5 sec 0.5 sec second ring 2 seconds data 3.579 mhz tcdl /358e tosc tdoc tpd tsup tcdh trd
33 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller xii. application circuit fig23. application circuit 1 2 34 a b c d 4 3 2 1 d c b a title number revision size a date: 18-may-1999 sheet of file: c:\advsch\78911_1.sch drawn by: tip ring det1 ringtime avss vss test cwtip gain common segment avdd vdd est st/gt pllc xin xout reset lcd display 0.22u 270k vdd 470k 33k 10k 10k 300k 100 32768 0.01u 27 0.1u 0.1u 0.1u 250v 0.1u 250v fuse 1000p 1000p tip ring to phone vss det1 vdd vss avss vss 27 100k 100k 470k npn 0.1u vdd matching network 10k 10k 103
34 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller : em78r911 spec. iv.pin configuration fig1. pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 seg40 seg41 seg42 seg43 test p80 p81 p82 p83 p84 p85 p86 p87 p90 p91 p92 p93 p94 p95 p96 p97 vdd nc gnd iod0 iod1 iod2 iod3 iod4 iod5 iod6 iod7 insend irsel ph1out x2out /hold /povd entcc mclk nc seg39 seg38 seg37 seg36 reset p77 p76 p75 p74 p73 p72 p71 p70 p67 p66 p65 p64 p63 p62 p61 p60 gnd nc vdd com7 com6 com5 com4 com3 vss2 com2 com1 com0 seg35 seg34 seg33 seg32 seg31 nc seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 gnd nc vdd cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 ca13 ca12 ca11 ca10 ca9 ca8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 nc avss dtmf pllc ringtime rdet1 ring tip cwring gain xin xout avdd seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 vdd nc gnd se10 se11 se12 se13 se14 se15 se16 vdd2 se17 se18 se19 eps ca-1 ca0
35 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller vi.pin descriptions pin i/o description vdd1,vdd2 avdd power digital power analog power vss1,vss2 avss power digital ground analog ground xtin i input pin for 32.768 khz oscillator xtout o output pin for 32.768 khz oscillator com0..com7 com8..com15 o o (port6) common driver pins of lcd drivers seg0...seg43 seg44..seg51 seg52..seg59 o o (port8) o (port9) segment driver pins of lcd drivers port9 as function key can wake up watchdog. pllc i phase loop lock capacitor tip i should be connected with tip side of twisted pair lines ring i should be connected with tip side of twisted pair lines cwtip i should be connected with tip side of twisted pair lines for cw. gain i op output pin for gain adjustment. rdet1 i detect the energy on the twisted pair lines . these two pins coupled to the twisted pair lines through an attenuating network. /ring time i determine if the incoming ring is valid.an rc network may be connected to the pin. int0 int1 int2 int3 port7(0) port7(1) port7(2) port7(3) port7(4:7) port7(0)~port7(3) signal can be interrupt signals. int2 and int3 has the same interrupt flag. io port p5.4 ~p7.7 port5 port 5 can be input or output port each bit. shared with lcd segment signals p6.0 ~p6.7 port6 port 6 can be input or output port each bit. shared with lcd common signals p7.0 ~p7.7 port7 port 7 can be input or output port each bit. internal pull high function. key scan function. p8.0 ~p8.7 port8 port 8 can be input or output port each bit. and shared with segment signal. p9.0 ~p9.7 port9 port 9 can be input or output port each bit. and can be set to wake up watch dog timer. and shared with segment signal. test i test pin into test mode , normal low dtmf o dtmf tone output reset i x2out o system clock output. ca-1 o ca-1 is used as address line to select low-order data (8 bits, through cd0~cd7) or high-order data (5 bits, through cd0~cd4) ers=1 => ca-1 no use ers=0 => ca-1=0 high order data
36 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller ca-1=1 low order data ers i input pin used to select the external rom data bus through bus cd0~d12 or cd0~cd7 only. high/low = cd0~cd12 / cd0~cd7. entcc i tcc control pin with internal pull-high (560k ? ? ? ? ). tcc works normally when entcc is high, and tcc counting is stopped when entcc is low. ca0~ca13 o program code address bus. ca0~ca13 are address output pins for external programming rom access. cd0~cd12 i data access in terms of ca0 ~ ca12 addressing. irsel o irsel is an output pin used to select an external even/odd rom. insend o used to indicate the instruction completion and ready for next instruction. /hold i microcontroller hold request. /povd i input pin used to enable power on voltage detector. power on voltage detector is enabled if /povd is low and is disabled if /povd is high. mclk i input pin for main clock selection. internal pull low through a register. rc4m o rc clock for program down load 4mpd i rc 4m power control pin. this pin pull low internally to enable clock. to pull high externally for disabling clock. iod0~iod7 o i/o data bus. ph1out o phase 1 output ix ac electrical characteristic tdiea delay from phase 3 end to insend active cl=100pf 30 ns tdiei delay from phase 4 end to insend inactive cl=100pf 30 ns tiew insend pulse width 30 ns tdca delay from phase 4 end to ca bus valid c1=100pf 30 ns tacc rom data access time 100 ns tcds rom data setup time 20 ns tcdh rom data hold time 20 ns tdca-1 delay time of ca-1 c1=100pf 30 ns note 1: n= selected prescaler ratio.
37 EM78911 EM78911 EM78911 EM78911 8 8 8 8- - - -bit micro bit micro bit micro bit micro- - - -cont roller cont roller cont roller cont roller clk 341234 12 3 /insend tdiea tdiei tiew tdca ca13:0 tacc tcds cd12:0 tcdh clk 341234 12 3 /insend tdiea tdiei tiew tdca ca13:0 tacc tcds cd7:0 tcdh ca-1 high order data low order data eps=0 ca-1=0 high order data ca-1=1 low order data eps=1 ca-1=disable tdca-1

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